1. Field of the Invention
The present invention generally relates to a semiconductor wafer having a multi-test circuit and to a method for manufacturing a semiconductor device including a multi-test process, and more particularly, to a semiconductor wafer having a multi-test circuit suitable for efficiently checking a plurality of chips formed on a wafer and a method for manufacturing a semiconductor device including a multi-test process suitable for efficiently checking the chips.
2. Description of the Background Art
During the process of manufacturing a semiconductor device, chips are checked when being formed on a wafer. In such a conventional wafer inspection, there has been commonly employed a method of checking the function of one chip or four chips at a time by bringing an inspection stylus into contact with input/output pads of an individual chip.
In the conventional wafer inspection method, when the inspection stylus is not properly brought into contact with the input/output pads of the chip, the stylus is repeatedly brought into contact with the input/output pads until an upright position is obtained. In this case, the input/output pads of the chip may be damaged in the course of wafer inspection. Further, a method of checking one chip or four chips at one time, such as a conventional wafer inspection method, requires a vast amount of time to check all the chips. In this respect, the conventional wafer inspection method has hindered a reduction in the cost of a semiconductor device.
The present invention has been conceived to solve the foregoing drawback in the conventional wafer inspection method, and the primary object of the present invention is to provide a semiconductor wafer having a multi-test circuit capable of efficiently checking a plurality of logic chips formed on a semiconductor wafer without damaging input/output pads of the chips.
The above object of the present invention is achieved by a semiconductor wafer. The semiconductor wafer includes a plurality of chips and a multi-test circuit for the purpose of testing the plurality of chips. The multi-test circuit includes a test circuit including input pads connected to terminals of the plurality of chips. The multi-test circuit further includes a plurality of output pads connected to respective output terminals of the plurality of chips. The test circuit and the output pads are provided in the peripheral area of the semiconductor wafer.
Another object of the present invention is to provide a method for manufacturing a semiconductor device including a multi-test process effective in efficiently checking a plurality of logic chips formed on a semiconductor wafer without damaging the input/output pads of the chips.
The above object of the present invention is achieved by a method for manufacturing a semiconductor device including a multi-test process. The method includes a step for forming a plurality of chips on a semiconductor wafer. The method also includes a step for forming a test circuit and a plurality of output pads. The test circuit includes input pads to be connected to terminals of the plurality of chips. The plurality of output pads is connected to respective output terminals of the plurality of chips. The test circuit and the output pads are provided in the peripheral area of the semiconductor wafer. The method further includes a multi-test process for testing the plurality of chips through use of the test circuit and the output pads, and a step for separating the plurality of chips after the multi-test process.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.